1. Field
One or more embodiments of the present invention relate to an organic light emitting display.
2. Description of Related Art
Recently, various flat panel displays (FPDs) capable of reducing weight and volume that are disadvantages of cathode ray tubes (CRTs) have been developed. The FPDs include liquid crystal displays (LCDs), field emission displays (FEDs), plasma display panels (PDPs), organic light emitting displays, and the like.
Among the FPDs, the organic light emitting display displays images using organic light emitting diodes (OLEDs) that generate light by the recombination of electrons and holes. The organic light emitting display has advantages of a high response speed while being driven with low power consumption.
The organic light emitting display includes a plurality of pixels arranged at crossing regions of data lines and scan lines in the form of a matrix. In general, each of the pixels includes an OLED, at least two transistors, and at least one capacitor.
In an organic light emitting display, an amount of current that flows to the OLED varies with the threshold voltage variation of the driving transistor included in each of the pixels and non-uniform displaying may therefore occur. That is, properties of the driving transistor, such as its threshold voltage, vary with the manufacturing process of the driving transistor included in each of the pixels, making it very difficult to manufacture all transistors of the organic light emitting display to have the same properties using current manufacturing technologies. Therefore, the threshold voltage variation of the driving transistors occurs.
In order to solve the above-mentioned problems, a pixel including six transistors and at least one capacitor was suggested in Korean Patent Publication No. 2007-0083072. The conventional pixel is coupled to a plurality of wiring lines including an initialization lines coupled to an initialization power source.
FIG. 1 is a view illustrating a related art wiring line structure for a group of sub pixels. In FIG. 1, for the sake of convenience, the internal structure of the sub pixels is omitted.
Referring to FIG. 1, related art sub pixels 2R, 2G, and 2B are located at crossing regions of data lines Di, Di+1, and Di+2, respectively, and a scan line Si. The red sub pixel 2R coupled to the ith data line Di and the ith scan line Si is additionally coupled to power source lines 10a and 10b and initialization lines 12a and 12b. 
Of the power source lines 10a and 10b, the first power source line 10a is parallel to the data line Di and receives power from a first power source ELVDD, which may be externally supplied. The first power source line 10a is electrically coupled to a transistor included in the red sub pixel 2R and supplies the voltage of the first power source ELVDD to the red sub pixel 2R.
Of the power source lines 10a and 10b, the second power source line 10b is parallel to the scan line Si and is electrically coupled to the first power source line 10a by a first contact hole 20. The second power source line 10b is coupled to the first power source line 10a to reduce or minimize a voltage drop of the first power source ELVDD.
Of the initialization lines 12a and 12b, the first initialization line 12a is parallel to the data line Di and is coupled to an initialization power source Vint. The first initialization line 12a is electrically coupled to a transistor included in the red sub pixel 2R and supplies a voltage of the initialization power source Vint to the red sub pixel 2R.
Of the initialization lines 12a and 12b, the second initialization line 12b is parallel to the scan line Si and is electrically coupled to the first initialization line 12a by a second contact hole 22. The second initialization line 12b is coupled to the first initialization line 12a to reduce or minimize a voltage drop of the initialization power source Vint.
However, since each of the above sub pixels 2R, 2G, and 2B is coupled to six wiring lines, a layout structure is complicated and an aperture ratio is reduced. For example, as each of the sub pixels 2R, 2G, and 2B is coupled to a plurality of wiring lines, yield is reduced so that manufacturing cost increases.